2013 ESEC!

ACROSSER Technology announces our participation in 2013 the Embedded Systems Expo and Conference (ESEC) from May 8th to the 10th. The event will take place at the Tokyo International Exhibition Center in Tokyo, Japan. We warmly invite all customers to come and meet us at the west hall, booth number: WEST 10-61.

(Software) Static analysis helps manage risk in Java

When it comes to software development, the old adage is best spun in a slightly different way: better "early" than never. Accordingly, static analysis can help those developing in Java to stay one step ahead of potential coding problems.

Today’s software development teams are under immense pressure; the market demands high-quality, secure releases at a constantly increasing pace while security threats become more and more sophisticated. Considering the high cost of product failures and security breaches, it is more important than ever to address these risks throughout the software development process. Potential problems need to be spotted early to prevent release delays or, worse, post-release failures.Fortunately, there are numerous tools to help developers manage these risks, helping to identify potential problems early in the development phase when issues are less disruptive and easier to fix. They are readily accessible to developers and easy to use within many development environments. This applies to developers programming in any language; however, we focus on Java in this discussion (see Sidebar 1).

Sidebar 1: Though Java’s mature ecosystem, numerous IDEs, and abundance of reference materials ease Java application development, they can also bestow a false sense of security upon developers, who should be watchful to mitigate Java’s weaknesses.

Static analysis helps mitigate risk

When considering static analysis tools for Java or otherwise, it is important to understand what these tools are. The term “static analysis” refers to the approach of analyzing a program without executing it. As we’ll see in the next section, static analysis tools can be used to produce reports on anything from coding standard violations to specific errors or vulnerabilities. Simply put, static analysis tools analyze source code to find information useful for managing risk.

One benefit of static analysis is that it can be performed early in the development cycle, often before the application will even execute. It is commonly integrated into an automated build, so that there is virtually no overhead to running frequent analyses. By integrating static analysis into the inner development loop, users maximize the value they get from such tools.

When used in conjunction with a well-designed development process, static analysis tools provide crucial visibility into the state of the software. This enables development teams to understand the level of risk in their code and where the risk resides so they can take action to mitigate or remove it entirely (Table 1). Individual tools generally focus on specific problems faced by software development teams, and teams often use a combination of these tools to get a comprehensive view of their development effort.

Table 1: Static analysis tools typically find specific types of issues, with each type representing a different class of risk and requiring a different type of action.

Developers have traditionally used static analysis tools via a simple IDE integration or as stand-alone tools. While the tools add significant value to the development effort, the proliferation of tools has created efficiency problems as developers spend more and more time using and maintaining different tools and sifting through more and more results. To wisely manage development resources, teams must be able to effectively manage, filter, and prioritize all those issues.

To address these problems, development testing platforms have emerged to unify and manage all of this static analysis information in one place, simplifying the user experience and increasing visibility and efficiency at larger scales while providing relevant access controls and reporting. Development testing platforms are even starting to blur the line between static analysis and other types of analysis by utilizing – during the static analysis process – artifacts generated during earlier program runs. For example, these platforms can use code coverage information from test runs during static analysis to effectively identify missing test cases automatically. The traditional approach to this problem requires significant manual effort based on simple coverage thresholds. By leveraging data from different sources, these platforms are able to significantly reduce the manual effort and time required to accomplish this with other methods.

Selecting static analysis tools for Java

The most popular, free, static analysis tools for Java are probably Checkstyle, PMD, and FindBugs. While they all fall under the “static analysis” umbrella, their strengths are so sufficiently different that many consider the tools to be complementary rather than alternatives.

Checkstyle

Checkstyle is billed as “a development tool to help programmers write Java code that adheres to a coding standard[1],” although it does not strictly limit itself to coding standard enforcement. It provides a documented API for users to define their own custom checks. Typical coding standards utilize basic rules to make code more readable and reduce the likelihood that future code changes will introduce bugs. Standards tend to define conventions about formatting (white space, bracketing, naming, commenting, and so on), inheritance, and visibility. When adequately enforced, well-designed coding standards can help developers reduce risk. Enforcement can be difficult, though, since coding standards generate a lot of violations and there can be significant pressure to ignore noisy rules. With legacy code, this can make enforcing new coding standards unfeasible. While most of the issues identified by Checkstyle do not affect code correctness, robustness, or performance, there is real value in helping developers quickly understand code written by others. It is not always obvious how to quantify the risk represented by these violations and it is problematic to measure risk directly from violation counts, but changes in those counts can be a reasonable proxy for changes in risk.

PMD

PMD is described as “…a source code analyzer. It finds unused variables, empty catch blocks, unnecessary object creation, and so forth[2].” It, too, is evolving and the current checks focus mainly on syntactic oddities that might belie developer mistakes, such as overcomplicated expressions, empty blocks, unused variables, parameters, and class members. It also has a popular module to identify duplicated code. Because it is generally reporting “suspicious code” as opposed to specific coding errors or standards violations, the user will need to carefully select the checks enabled for everyday use. Because enforced rules are selected by the user, this tool can be useful for both legacy and greenfield projects, and it is often easy to correlate these counts with risk. Unfortunately, it might not be obvious whether reported issues should be considered defects or maintenance concerns.

FindBugs

FindBugs is probably the most popular of these tools. It looks for actual bugs in the code, as well as suspicious code and standards violations. Because of the wide range of reported issues, it is important to use a configuration that includes the most relevant checks for the project. This is especially true for legacy projects, as it’s easier to keep new projects clean from the beginning. Like PMD, any team can benefit from using FindBugs and associating issue counts to risk can be straightforward.

Commercial static analysis tools show similar diversity, identifying everything from standards violations to actual defects and security vulnerabilities. To illustrate how a commercial tool might compare to a free tool, I analyzed version 1.496 of the Jenkins job management system (www.jenkins-ci.org) using a proprietary static analysis solution and version 2.0.1 of FindBugs, with all checks enabled. On this code base, 852 unique issues were identified – with only 28 issues identified by both products. The proprietary solution found 197 unique issues, with 188 of those coming from high-impact categories (security and concurrency bugs, resource leaks, and unhandled exceptions like null dereferences). FindBugs found 627 unique issues, with 29 coming from those high-impact categories. In short, each of the tools found significant high-impact issues missed by the others, so using a proprietary solution or FindBugs alone will leave significant risk undetected.

Development testing – Tying it all together

Static analysis tools are a powerful ally in the software development effort for Java developers, as these tools enable developers to gain insight into risk throughout the software development life cycle. They are typically easy to automate, enabling users to spend their time fixing problems rather than running the tools.

When it comes to managing risk, more information is generally better – as long as that information illuminates actual sources of risk that developers care about. When deciding which tools to adopt, remember to consider not just the types of issues that analysis tools identify, but how those tools can work together to provide additional value. Also, be sure to configure them appropriately so that the number of issues doesn’t overwhelm your users.

Modern development testing platforms take testing tools to another level by unifying the data in one place, simplifying the user experience, and creating opportunities to provide even more value.

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refer to: http://embedded-computing.com/articles/static-helps-manage-risk-java/ 

AMD Embedded G-Series APU to bring the optimum combination of computing power

A new All-in-One Gaming Board, the AMB-A55EG1. AMB-A55EG1 features AMD Embedded G-Series T56N 1.65GHz dual-core APU, two DDR3-1333 SO-DIMM, which provides great computing and graphic performance is suitable for casino gaming and amusement applications. It is designed to comply with the most gaming regulations including GLI, BMM, and Comma 6A. AMB-A55EG1 is specifically designed to be a cost competitive solution for the entry-level gaming market.

In conclusion, AMB-A55EG1 bridges Acrosser’s innovated gaming solutions and AMD Embedded G-Series APU to bring the optimum combination of computing power, graphic performance, and gaming features. Acrosser supports all gaming products in Windows XP Pro, XP embedded and mainstream Linux operation system with complete software development kit (SDK).  In addition, Acrosser’s gaming platforms have a minimum 5-year availability to fulfill the demand of long term supply in gaming industry.

Contact：
http://www.acrosser.com/inquiry.html

Milestone events in the EDA industry

This seems to be the year for milestone events in the EDA industry, though calculations show some of the “anniversary” designations to be premature. Nevertheless, the first big EDA event of the year is the Design and Verification Conference (DVCon), held in San Jose, CA every February. DVCon celebrated its 10th anniversary this year, after a transformation from HDLcon in 2003, which followed the earlier union of the VHDL International User’s Forum and International Verilog HDL Conference. Those predecessor conferences trace their origins back 25 years and 20 years, respectively.

After DVCon, EDA marketers quickly turn to preparations for the June Design Automation Conference (DAC), perhaps with a warm-up at Design, Automation, and Test in Europe (DATE) in March. DAC is the big show, however, and this year marks the 50th such event (and its 49th anniversary). Phil Kaufman Award winner Pat Pistilli received the EDA industry’s’ highest honor for his pioneer work in creating DAC, which grew from his amusingly-named Society to Help Avoid Redundant Effort (SHARE) conference in 1964.

Milestones inevitably lead to some reflection, but also provide an opportunity to look forward to what the future will bring. In our 2nd annual EDA Digest Resource Guide, we will be asking EDA companies to share what they see as the biggest challenges facing the industry in the next five years, and how the industry will change to meet those challenges. Will future innovations be able to match the impact of the greatest past developments in EDA, which enabled the advances in electronics that we benefit from today?


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refer to : http://dsp-fpga.com/articles/looking-back-at-the-milestones-as-dac-50-approaches/

AIS Introduces Low Cost Industrial Touch Screen Display Monitor

American Industrial Systems Inc. (AIS), has introduced a complete line of industrial touchscreen LCD monitors in several mechanical designs and paired with the latest in touchscreen technology to fit every situation.

IRVINE, CA -- American Industrial Systems Inc. (AIS), has introduced a complete line of industrial touchscreen monitors in several mechanical designs and paired with the latest in touchscreen technology to fit every situation. The monitors are currently available in open frame,chassis, panel mount, IP65 mount bezel, and rack mount to cover most industrial requirements. Also available are AIS’ rugged touchscreen display line, built to handle the most extreme of environments, which include vehicle mount touch screen display, Full IP65, and Marine grade touchscreen bridge displays. The need for touchscreen HMI displays in today’s market is growing in every industry whether it is retail, digital signage, military, industrial, or gaming; AIS’ has the products, technology, and price competitiveness to bring you to market faster.

AIS touchscreen displays utilize industrial grade components and are encased in steel, aluminum, or aluminum-magnesium alloys for maximum reliability and protection from shock/vibration, Wide Temperature Range Operation and harsh environmental conditions. Add-on enhancements are available such customize the LCD to perfectly fit applications such as sunlight readable touchscreen LCD enhancements, wide voltage range inputs, Anti-corrosion coatings, IP65 Water/Dustproof rating, and Touch screen integration. Several touchscreen technologies are available including resistive, capacitive, infra red (IR), surface acoustic wave (SAW), and 3M MicroTouch™ DST Touch System for Large size screens. Together AIS has thousands of pre-engineered, documented and tested touch screen LCD solutions at cost effective prices.

Features & Benefits:

• Industrial Grade Displays

• Ruggedized Housings

• 6.4” to 42” in Size

• IP65 Water and Dustproof Rating

• Sunlight Readability Enhancements

• Transflective Passive Enhancements

• High Brightness Displays

Touch screen Technology

o Resistive Touch Screen Technology

o The cost effective workhorse of touch technologies

o Surface Acoustic Wave (SAW) Touch Screen Technology

o Superior optical characteristics for best clarity

o Capacitive Touch Screen Technology

o Durable, cost effective solution, impervious to on-screen contaminants

o Infrared Touch Screen Technology

o Suitable for harsh environments and outdoor applications

o Large touch screens for digital signage

About American Industrial Systems Inc.

refer to :

http://industrial-embedded.com/news/ais-gaming-digital-signage-industries/0/

Communications networking....

IT managers are under increasing pressure to boost network capacity and performance to cope with the data deluge. Networking systems are under a similar form of stress with their performance degrading as new capabilities are added in software. The solution to both needs is next-generation System-on-Chip (SoC) communications processors that combine multiple cores with multiple hardware acceleration engines.

The data deluge, with its massive growth in both mobile and enterprise network traffic, is driving substantial changes in the architectures of base stations, routers, gateways, and other networking systems. To maintain high performance as traffic volume and velocity continue to grow, next-generation communications processors combine multicore processors with specialized hardware acceleration engines in SoC ICs.

The following discussion examines the role of the SoC in today’s network infrastructures, as well as how the SoC will evolve in coming years. Before doing so, it is instructive to consider some of the trends driving this need.

Networks under increasing stress

In mobile networks, per-user access bandwidth is increasing by more than an order of magnitude from 200-300 Mbps in 3G networks to 3-5 Gbps in 4G Long-Term Evolution (LTE) networks. Advanced LTE technology will double bandwidth again to 5-10 Gbps. Higher-speed access networks will need more and smaller cells to deliver these data rates reliably to a growing number of mobile devices.

In response to these and other trends, mobile base station features are changing significantly. Multiple radios are being used in cloud-like distributed antenna systems. Network topologies are flattening. Operators are offering advanced Quality of Service (QoS) and location-based services and moving to application-aware billing. The increased volume of traffic will begin to place considerable stress on both the access and backhaul portions of the network.

Traffic is similarly exploding within data center networks. Organizations are pursuing limitless-scale computing workloads on virtual machines, which is breaking many of the traditional networking protocols and procedures. The network itself is also becoming virtual and shifting to a Network-as-a-Service (NaaS) paradigm, which is driving organizations to a more flexible Software-Defined Networking (SDN) architecture.

These trends will transform the data center into a private cloud with a service-oriented network. This private cloud will need to interact more seamlessly and securely with public cloud offerings in hybrid arrangements. The result will be the need for greater intelligence, scalability, and flexibility throughout the network.

Moore’s Law not keeping pace

Once upon a time, Moore’s Law – the doubling of processor performance every 18 months or so – was sufficient to keep pace with computing and networking requirements. Hardware and software advanced in lockstep in both computers and networking equipment. As software added more features with greater sophistication, advances in processors maintained satisfactory levels of performance. But then along came the data deluge.

In mobile networks, for example, traffic volume is growing by some 78 percent per year, owing mostly to the increase in video traffic. This is already causing considerable congestion, and the problem will only get worse when an estimated 50 billion mobile devices are in use by 2016 and the total volume of traffic grows by a factor of 50 in the coming decade.

In data centers, data volume and velocity are also growing exponentially. According to IDC, digital data creation is rising 60 percent per year. The research firm’s Digital Universe Study predicts that annual data creation will grow 44-fold between 2009 and 2020 to 35 zettabytes (35 trillion gigabytes). All of this data must be moved, stored, and analyzed, making Big Data a big problem for most organizations today.

With the data deluge demanding more from network infrastructures, vendors have applied a Band-Aid to the problem by adding new software-based features and functions in networking equipment. Software has now grown so complex that hardware has fallen behind. One way for hardware to catch up is to use processors with multiple cores. If one general-purpose processor is not enough, try two, four, 16, or more.

Another way to improve hardware performance is to combine something new – multiple cores – with something old – Reduced Instruction Set Computing (RISC) technology. With RISC, less is more based on the uniform register file load/store architecture and simple addressing modes. ARM, for example, has made some enhancements to the basic RISC architecture to achieve a better balance of high performance, small code size, low power consumption, and small silicon area, with the last two factors being important to increasing the core count.

Hardware acceleration necessary, but …

General-purpose processors, regardless of the number of cores, are simply too slow for functions that must operate deep inside every packet, such as packet classification, cryptographic security, and traffic management, which is needed for intelligent QoS. Because these functions must often be performed in serial fashion, there is limited opportunity to process them simultaneously in multiple cores. For these reasons, such functions have long been performed in hardware, and it is increasingly common to have these hardware accelerators integrated with multicore processors in specialized SoC communications processors.

The number of function-specific acceleration engines available also continues to grow, and more engines (along with more cores) can now be placed on a single SoC. Examples of acceleration engines include packet classification, deep packet inspection, encryption/decryption, digital signal processing, transcoding, and traffic management. It is even possible now to integrate a system vendor’s unique intellectual property into a custom acceleration engine within an SoC. Taken together, these advances make it possible to replace multiple SoCs with a single SoC in many networking systems (see Figure 1).

Figure 1: SoC communications processors combine multiple general-purpose processor cores with multiple task-specific acceleration engines to deliver higher performance with a lower component count and lower power consumption. (Click graphic to zoom by 1.9x)

In addition to delivering higher throughput, SoCs reduce the cost of equipment, resulting in a significant price/performance improvement. Furthermore, the ability to tightly couple multiple acceleration engines makes it easier to satisfy end-to-end QoS and service-level agreement requirements. The SoC also offers a distinct advantage when it comes to power consumption, which is an increasingly important consideration in network infrastructures, by providing the ability to replace multiple discrete components in a single energy-efficient IC.

The powerful capabilities of today’s SoCs make it possible to offload packet processing entirely to system line cards such as a router or switch. In distributed architectures like the IP Multimedia System and SDN, the offload can similarly be distributed among multiple systems, including servers.

Although hardware acceleration is necessary, the way it is implemented in some SoCs today may no longer be sufficient in applications requiring deterministic performance. The problem is caused by the workflow within the SoC itself when packets must pass through several hardware accelerators, which is increasingly the case for systems tasked with inspecting, transforming, securing, and otherwise manipulating traffic.

If traffic must be handled by a general-purpose processor each time it passes through a different acceleration engine, latency can increase dramatically, and deterministic performance cannot be guaranteed under all circumstances. This problem will get worse as data rates increase in Ethernet networks from 1 Gbps to 10 Gbps, and in mobile networks from 300 Mbps in 3G networks to 5 Gbps in 4G networks.

Next-generation multicore SoCs

LSI addresses the data path problem in its Axxia SoCs with Virtual Pipeline technology. The Virtual Pipeline creates a message-passing control path that enables system designers to dynamically specify different packet-processing flows that require different combinations of multiple acceleration engines. Each traffic flow is then processed directly through any engine in any desired sequence without intervention from a general-purpose processor (see Figure 2). This design natively supports connecting different heterogeneous cores together, enabling more flexibility and better power optimization.

Figure 2: To maximize performance, next-generation SoC communications processors process packets directly and sequentially in multiple acceleration engines without intermediate intervention from the CPU cores. (Click graphic to zoom)

In addition to faster, more efficient packet processing, next-generation SoCs also include more general-purpose processor cores (to 32, 64, and beyond), highly scalable and lower-latency interconnects, nonblocking switching, and a wider choice of standard interfaces (Serial RapidIO, PCI Express, USB, I2C, and SATA) and higher-speed Ethernet interfaces (1G, 2.5G, 10G, and 40G+). To easily integrate these increasingly sophisticated capabilities into a system’s design, software development kits are enhanced with tools that simplify development, testing, debugging, and optimization tasks.

Next-generation SoC ICs accelerate time to market for new products while lowering both manufacturing costs and power consumption. With deterministic performance for data rates in excess of 40 Gbps, embedded hardware is once again poised to accommodate any additional capabilities required by the data deluge for another three to four years.

refer:http://embedded-computing.com/articles/next-generation-architectures-tomorrows-communications-networks/

About wireless networks

802.11 networks are becoming nearly ubiquitous in many enterprise settings and can often be tapped to solve embedded problems in the same location. In this example, a logistics cart used for warehouse operations becomes 802.11 enabled, improving the efficiency of a critical process.

In a tough economy with increased competition from global markets, companies are forced to do more with less. Supply chain management is one area where companies realize this challenge. Organizations are continually struggling to ship more orders, decrease processing time, and increase order accuracy, all the while reducing costs. The nature of order processing has changed as well. With just-in-time and lean manufacturing techniques becoming common practices, distribution warehouses often need to process a high volume of small orders, which often involve a large mix of products, adding further complexity to the process.

The end result is that the order picking process is increasingly challenging. In a typical warehouse or distribution center, studies have shown that order picking can consume as much as two-thirds of the facility’s operating cost and time. As a result, companies are continually looking for new technologies and innovations to automate the order picking process.


refer: http://embedded-computing.com/articles/wireless-networks-provide-with-less/